1. Field of the Invention
This invention relates generally to semiconductor devices and fabrication methods therefor, and more particularly, to a semiconductor device having bit lines formed in a semiconductor substrate and a fabrication method therefor.
2. Description of the Related Art
In recent years, data-rewritable, non-volatile memory semiconductor devices have been widely used. Technical developments downsizing the memory cells of such non-volatile memory semiconductor devices are being promoted to obtain higher storage capacity. For example, there have been developed flash memories having an Oxide/Nitride/Oxide (ONO) film such as Metal Oxide Nitride Oxide Silicon (MONOS) or Silicon Oxide Nitride Oxide Silicon (SONOS).
Among such memories, there has been developed a flash memory in which one memory cell transistor has two or more charge storage regions to obtain higher storage capacity. As disclosed in Japanese Patent Application Publication No. 2000-514946 (hereinafter, referred to as conventional art), a memory cell transistor has two charge storage regions between the gate electrode and the semiconductor substrate. In this transistor, the source and the drain are switchable for symmetrical operation, creating a structure wherein the source and the drain are indistinguishable. Also, the bit lines are embedded in the semiconductor substrate and coupled to the source and drain and can act as either a source region or a drain region, thereby achieving miniaturization of the memory cell.
Referring to FIGS. 1(a) through 1(e), a description will be given of a conventional fabrication method of memory cells in accordance with the afore-described conventional art. In FIG. 1(a), a tunnel oxide film (silicon oxide film) 12, a trap layer (silicon nitride film) 14, and a top oxide film (silicon oxide film) 16 are formed on a P-type semiconductor substrate 10, as an ONO film 18. In FIG. 1(b), a photoresist 50 is applied to form openings in accordance with generally used lithography techniques.
In FIG. 1(c), arsenic ions, for example, are implanted in the substrate 10 by using the photoresist 50 serving as a mask to form bit lines 20. Pocket injection is performed using the photoresist 50 serving as a mask to form pocket injection regions 22. Pocket injection is a method of forming a P-type region having a concentration higher than that of the P-type semiconductor substrate 10, by injecting, for example, boron obliquely to a vertical direction of the semiconductor substrate 10. This realizes a steep junction profile near the bit line 20, improving writing characteristics of the memory cell.
In FIG. 1(d), the photoresist 50 is removed. And in FIG. 1(e), a word line 24 is formed on the ONO film 18. Subsequently, an interlayer insulating film, a metal line, and a protection film are formed, and a flash memory is thus fabricated.
According to the conventional art, a non-volatile memory device is configured such that the semiconductor substrate 10 provided between the bit lines (source/drain regions) 20 functions as a channel, and the charge is stored in the trap layer 14 of the ONO film 18 provided between the channel and the word line (gate electrode) 24. There are two charge storage regions between the bit lines 20 below the word line 24.
The charge is stored in the ONO film 18 by applying a high electric field between the source region and the drain region (namely, between the bit lines 20) and injecting electrons having high energy into the trap layer 14 in the ONO film 18. Data is erased by injecting holes having high energy into the trap layer 14. Therefore, there is a need for forming the shallow bit lines 20 and a steep junction profile in order to improve writing and erasing characteristics.
In addition, as the bit lines 20 are formed in diffusion regions, they have a higher resistance than that of a metal. Accordingly, the writing and erasing characteristics are degraded. For this reason, the bit lines 20 are connected to the metal line (above the word line 24 and the interlayer insulating film) by contact holes formed in the interlayer insulating film across every several word lines 24.
In the conventional art, the memory cell can be downsized by reducing the resistance of the bit line 20. As the resistance of the bit line 20 is reduced, the bit line width can be reduced because the number of the contact holes, each of which connects the bit line 20 and the metal line, can be reduced.
The resistance of the bit line 20 can be decreased by increasing the ion implantation energy or dose when the bit line 20 is formed. However, an increase in the ion implantation dose increases a junction leakage current between the bit line 20 and the semiconductor substrate 10. In other words, if the resistance of the bit line is decreased to downsize the memory cell, the junction leakage current will be increased, thereby degrading the transistor characteristic of the memory cell.
Thus, to improve the writing and erasing characteristics, there is a need for forming shallow source/drain regions (namely, the bit lines 20) and the steep junction profile. However, such shallow source/drain regions (the bit lines 20) increase the resistance of the bit line 20, running counter to the above-described goal of miniaturization of the memory cell.